1. Field of the Invention
The present invention relates to determining when to flush a second level cache based on recognizing a special flush acknowledge bus cycle executed by the microprocessor of a computer system.
2. Description of the Related Art
The computer industry is a growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful computers. A major bottleneck in computer speed has historically been the speed with which data can be accessed from memory, where this speed is referred to as the memory access time. The microprocessor, with its relatively fast processor cycle times, has generally had to wait during memory accesses to account for the relatively slow memory devices. Therefore, improvement in memory access times has been one of the major areas of research in enhancing computer performance.
In order to bridge the gap between fast processor cycle times and slow memory access times, cache memory was developed. A cache is a small amount of very fast, expensive, zero wait state memory that is used to store a copy of frequently accessed code and data from system memory. The microprocessor can operate out of this very fast memory and thereby reduce the number of wait states that must be interposed during memory accesses.
There are generally two types of cache memory systems: write-through and write-back. In a write-back cache design, the writes are performed only to the cache, with the cache only providing the information to the system when another party requests the address. Thus, when a write "hit" occurs in a write-back cache indicating the cache has data stored for the indicated address, the cache location is updated with the new data, but the write operation is not broadcast to the system memory. In this instance, the cache holds a modified copy of the data and assumes the responsibility providing this modified copy to other requesting devices. When the cache is holding modified data, the corresponding memory locations in system memory are now said to hold incorrect or dirty data. When a cache flush occurs, a write-back cache must write back all modified locations to system memory before the entire cache contents are invalidated.
In a write-through cache design, all writes are often stored in a cache and are always broadcast to the memory. For a write-through cache, the microprocessor, during every memory write cycle, writes the data to the cache as well as to the main memory so that the main memory does not contain obsolete information. Thus, when a cache flush occurs for a write-through cache, the data does not have to be written back to the main memory. A series of tag random access memories (RAMs), typically accompanying the cache RAM, contains "tags" or a copy of the upper address bits of the memory address of the data contained in the cache, and also valid bits used to identify whether the data located by a tag address is valid or not. To flush a write-through cache, it is only necessary to clear the valid bits in the tag RAMs, since none of the data need be written to main memory.
The management or control of the cache is generally performed by a device referred to as a cache controller. The cache controller is principally responsible for keeping track of the contents of the cache as well as controlling data movement into and out of the cache. Another responsibility of the cache controller is the preservation of cache coherency, which refers to the requirement that the copy of system memory held in the cache be identical to the data held in the system memory. In some systems, a write-back cache is contained within the microprocessor so that the microprocessor performs the cache controller functions described above for its internal cache. The microprocessor with an internal cache also usually includes a pin to receive a flush signal, where the microprocessor responds by flushing its internal cache.
In a typical computer system, a microprocessor, such as the i486 microprocessor manufactured by the Intel Corporation (Intel), is coupled to cache memory and to a cache controller, such as the C5 cache controller, also by Intel. The cache controller and the cache memory are typically connected between the microprocessor and a host bus and the main memory is typically connected to the host bus. The microprocessor typically includes an internal cache so that the external cache memory is a second level, or level two cache. Thus, the microprocessor operates out of its internal cache until a miss occurs, and then it operates out of the second level cache. If a cache miss occurs in the second level cache, the microprocessor executes a cycle to the host bus to access the main memory.
Another block of logic, referred to as miscellaneous central processing unit (CPU) logic, is coupled to the microprocessor, to the cache controller and to the host bus to provide support for the microprocessor. The miscellaneous CPU logic also determines cache flush conditions, and generally includes numeric coprocessor logic, processor reset generation logic, cache support logic, input/output (I/O) registers and parity error logic as well as other miscellaneous logic. Concerning its cache duties, the miscellaneous CPU logic monitors the host bus cycles and asserts a flush signal to the microprocessor so that the microprocessor responds by flushing its internal cache. The miscellaneous CPU logic may also provide a flush signal to the cache controller, where the cache controller responds by asserting a flush signal to the second level cache. The CPU and cache controller flush signals may be the same or different signals, depending upon whether there are different conditions for flushing the internal cache versus the second level cache. In any event, the cache controller also includes an input pin to receive a flush command and an output pin to flush or invalidate the cache memory.
There are several conditions that are monitored on the host bus by the miscellaneous CPU logic to determine when to flush the respective caches. One condition is a write operation to a certain I/O port, typically referred to as a processor control port, to set a flush bit to initiate an orderly flush procedure. Another condition is when a cache enable bit is negated after the bit had previously been set. The microprocessor may also execute cache invalidate instructions, where the microprocessor invalidates its internal cache, so that the second level cache is also flushed. Several signals on the host bus, including a host memory-I/O signal indicating an I/O cycle rather than a memory cycle, a host data-control signal indicating a control cycle rather than a data cycle, a host read-write signal indicating a write rather than a read cycle and byte enable bits HBE3*-HBE0* indicating a flush instruction, are all used to determine whether a cache invalidate instruction has been issued. Another condition is when write operations are executed to a RAM relocation register, typically residing at the address 80C00000h, which causes flushing of both of the caches. A lower case h at the end of an address designates hexadecimal notation.
The P5 or Pentium microprocessor from Intel is a next generation microprocessor which has very high performance including superscalar architecture and integrated and separate code and data caches. The P5 uses a full 64-bit data path and provides significant performance improvements over the 32-bit data path used in i386 and i486 based computers. The P5 has an internal write-back data cache as well as a flush input pin for receiving a flush signal to command the P5 to flush its internal caches. The P5 also executes a new flush acknowledge special cycle after performing the write-back flush cycles, if any, to inform external devices that it has completed its flush operation of the data cache.
It is desirable in the P5 microprocessor environment to eliminate as many pins on the cache controller as possible, including the flush input to the cache controller of the second level cache.